A flat panel display unit such as a plasma display is normally driven by a high voltage of about 100 V to 300 V. When such a flat panel display unit is controlled by a CMOS level signal having a logical amplitude of about 5 V, the unit cannot be directly driven by this logic signal. Therefore, a driver circuit for converting the CMOS level signal into a high-voltage level is required.
FIG. 7 is a circuit diagram showing the arrangement of a driver circuit used for the above purpose. This driver circuit possesses a function for determining the level of an output signal Out on the basis of an input signal In and a control signal cont. The circuit shown in FIG. 7 also has a function for setting the output state at a high-impedance state.
Referring to FIG. 7, reference numerals 51 to 54 denote double diffusion n-channel MOS transistors each having a structure of with a high withstand voltage; 55, a CMOS AND gate consisting of enhancement p- and n-channel MOS transistors; 56, an inverter; 57, a current setting resistor; 58, a pnp multicollector transistor; 59, a Zener diode for bias voltage generation; 60, an output terminal; and 61, a load capacitor corresponding to one segment of the flat panel display unit and connected to the output terminal 60. Reference symbol V.sub.DD denotes a power source voltage of, e.g., 5 V of a logical system; V.sub.CC, a power source voltage of, e.g., 300 V for a high-voltage system; and GND, a ground voltage of 0 V for the logical and high-voltage systems. The resistor 57 and the transistor 54 constitute a reference voltage generator 62 for generating a predetermined reference voltage Vref from the power source voltage V.sub.DD of the logical system. The reference voltage Vref, generated by the reference voltage generator 62, is supplied to the AND gate 55 as a power source voltage. The AND gate 55 also receives the input signal In and the control signal Cont. An output from the AND gate 55 is supplied to the gate of the transistor 53.
When both the input signal In and the control signal Cont are set at "1" level, an output signal from the AND gate 55 is also set at "1" level, i.e., at the reference voltage Vref. At this time, a drain current determined by the resistance of the resistor 57 and having the same value as that of the transistor 54 flows in the transistor 53. As a result, the multicollector transistor 58 is turned ON, and a predetermined Zener voltage appears at the cathode of the Zener diode 59 as a consequence of a current flowing out from one of the collectors of the multicollector transistor 58. If the value of the Zener voltage of the Zener diode 59 is set to the threshold voltage of the transistor 51 or higher, the transistor 51 is turned ON. Thus, when both the input signal In and the control signal Cont are set at "1" level, the output signal Out is set at "1" level, i.e., the V.sub.CC level, by means of the ON transistor 51.
However, when both the input signal In and the control signal Cont are set at "0" level, an output signal from the AND gate 55 is set at "0" level, and the transistor 53 is turned OFF. In this case, an output signal from the inverter 56 is set at "1" level, and then the transistor 52 is turned ON. As a result, the output terminal 60 is discharged through the Zener diode 59 and the ON transistor 52, and the output signal out is set at "0" level, i.e., the GND level.
When the input signal In is set at "1" level and the control signal Cont is set at "0" level, the transistors 51 and 52 are both turned OFF, and the output signal Out is set in a high-impedance state.
In the conventional circuit described above, the reference voltage Vref is always generated by the reference voltage generator 62 and a constant current flows therethrough. For this reason, however, when the output signal Out is to be set to "1" level, current continues flowing unnecessarily through the generator 62 after the level of the output signal Out goes to the V.sub.CC level, resulting in energy waste.
Since, in the conventional circuit, each transistor constituting the AND gate 55 is operated by means of the voltage Vref, which is lower than the power source voltage V.sub.DD of 5 V for the logical system, the control range of the threshold voltage is very narrow. Because of this, it is very difficult to design an optimum circuit arrangement.
In addition, when, in the case of the conventional circuit, the output signal Out is switched from "1" level to "0" level, the transistors 51 and 52 are simultaneously turned on for a given time interval due to a delay in the cut-off operation of the transistor 51. During this time interval, a short-circuiting current flows from the power source voltage Vcc of the high-voltage system to the ground voltage GND. Since the level of the power source voltage Vcc of the high-voltage system is very high, i.e., 300 V, a considerable amount of power is consumed even when the time interval during which the short-circuiting current flows is very short. In the worst case, this short-circuiting current may cause the transistors 51 and 52 to break down.
Moreover, the conventional circuit has another disadvantage in that the switching of the output signal Out from "1" level to the high-impedance state takes place at a relatively slow speed. More specifically, when the multicollector transistor 58 is kept ON, and the output signal Out is set at "1" level, the predetermined Zener voltage is generated at the cathode of the Zener diode 59. Even if the multicollector transistor 58 is turned OFF, the cathode potential does not immediately drop, since there is no discharge path to the ground voltage at the cathode of the Zener diode 59. Thus, the timing for switching OFF the transistor 51 is drawn out, in turn increasing the time required to switch the output signal Out to the high-impedance state.
As described above, the conventional driver circuit has a number of disadvantages: current consumption is high, the control range of the threshold voltage of a transistor is very narrow, resulting in difficulties with regard to circuit design, a short-circuiting current flows between the power sources, and can easily cause transistor breakdown due to a consequent delay in transistor switching operation, with the result that the time required for switching the output signal from "1" level to the high-impedance state is increased.
The present invention has been developed in consideration of the above, and has as its object to provide a driver circuit the design of which can be optimized, the operating speed of which is increased, and wherein current consumption is reduced.